ispLEVER Classic 1.3.00.09.29.09 Fitter Report File

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Project Name : isa2can Project Path : D:\Projects\SB-iGLX\04-Software\CAN-CPLD Project Fitted on : Tue Sep 08 11:37:49 2009 Device : M4032_32 Package : 48 GLB Input Mux Size : 6 Available Blocks : 2 Speed : -7.5 Part Number : LC4032V-75T48C Source Format : ABEL_Schematic Project 'isa2can' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.05 secs Partition Time 0.00 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 14 Total Logic Functions 6 Total Output Pins 6 Total Bidir I/O Pins 0 Total Buried Nodes 0 Total Flip-Flops 0 Total D Flip-Flops 0 Total T Flip-Flops 0 Total Latches 0 Total Product Terms 6 Total Reserved Pins 0 Total Locked Pins 20 Total Locked Nodes 0 Total Unique Output Enables 0 Total Unique Clocks 0 Total Unique Clock Enables 0 Total Unique Resets 0 Total Unique Presets 0 Fmax Logic Levels - Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 0 4 --> 0 I/O / Enable Pins 2 2 0 --> 100 I/O Pins 30 18 12 --> 60 Logic Functions 32 6 26 --> 18 Input Registers 32 0 32 --> 0 GLB Inputs 72 14 58 --> 19 Logical Product Terms 160 6 154 --> 3 Occupied GLBs 2 2 0 --> 100 Macrocells 32 6 26 --> 18 Control Product Terms: GLB Clock/Clock Enables 2 0 2 --> 0 GLB Reset/Presets 2 0 2 --> 0 Macrocell Clocks 32 0 32 --> 0 Macrocell Clock Enables 32 0 32 --> 0 Macrocell Enables 32 0 32 --> 0 Macrocell Resets 32 0 32 --> 0 Macrocell Presets 32 0 32 --> 0 Global Routing Pool 68 14 54 --> 20 GRP from IFB .. 14 .. --> .. (from input signals) .. 14 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 0 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 3 11 14 5/16 0 6 0 10 6 6 GLB B 0 0 0 13/16 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- TOTALS: 3 11 14 18/32 0 6 0 26 6 6 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name -------------------------------------------------------------------------- 1 | TDI | - | | | | | 2 | I_O | 0 | A5 | | | | 3 | I_O | 0 | A6 | | | | 4 | I_O | 0 | A7 | | | | 5 |GNDIO0 | - | | | | | 6 |VCCIO0 | - | | | | | 7 | I_O | 0 | A8 | | | | 8 | I_O | 0 | A9 | | | | 9 | I_O | 0 | A10| | | | 10 | I_O | 0 | A11| | | | 11 | TCK | - | | | | | 12 | VCC | - | | | | | 13 | GND | - | | | | | 14 | I_O | 0 | A12| * |LVCMOS18 | Output|SJA_ALE 15 | I_O | 0 | A13| * |LVCMOS18 | Output|SJA_RDn 16 | I_O | 0 | A14| * |LVCMOS18 | Output|SJA_WRn 17 | I_O | 0 | A15| * |LVCMOS18 | Output|SJA_CSn 18 |INCLK1 | 0 | | | | | 19 |INCLK2 | 1 | | | | | 20 | I_O | 1 | B0 | | | | 21 | I_O | 1 | B1 | | | | 22 | I_O | 1 | B2 | * |LVCMOS18 | Input |ISA_RSTDRV 23 | I_O | 1 | B3 | * |LVCMOS18 | Input |SJA_INTn 24 | I_O | 1 | B4 | * |LVCMOS18 | Input |ISA_IOWn 25 | TMS | - | | | | | 26 | I_O | 1 | B5 | * |LVCMOS18 | Input |ISA_IORn 27 | I_O | 1 | B6 | * |LVCMOS18 | Input |ISA_SA0 28 | I_O | 1 | B7 | * |LVCMOS18 | Input |ISA_SA2 29 |GNDIO1 | - | | | | | 30 |VCCIO1 | - | | | | | 31 | I_O | 1 | B8 | * |LVCMOS18 | Input |ISA_SA3 32 | I_O | 1 | B9 | * |LVCMOS18 | Input |ISA_SA4 33 | I_O | 1 | B10| * |LVCMOS18 | Input |ISA_SA5 34 | I_O | 1 | B11| * |LVCMOS18 | Input |ISA_SA6 35 | TDO | - | | | | | 36 | VCC | - | | | | | 37 | GND | - | | | | | 38 | I_O | 1 | B12| * |LVCMOS18 | Input |ISA_SA7 39 | I_O | 1 | B13| * |LVCMOS18 | Input |ISA_SA8 40 | I_O | 1 | B14| * |LVCMOS18 | Input |ISA_SA9 41 | I_O/OE| 1 | B15| * |LVCMOS18 | Input |AEN 42 |INCLK3 | 1 | | | | | 43 |INCLK0 | 0 | | | | | 44 | I_O/OE| 0 | A0 | * |LVCMOS18 | Output|SJA_RSTn 45 | I_O | 0 | A1 | | | | 46 | I_O | 0 | A2 | | | | 47 | I_O | 0 | A3 | * |LVCMOS18 | Output|ISA_IRQ 48 | I_O | 0 | A4 | | | | -------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal --------------------------------------- 41 B I/O 1 A- Up AEN 26 B I/O 1 A- Up ISA_IORn 24 B I/O 1 A- Up ISA_IOWn 22 B I/O 1 A- Up ISA_RSTDRV 27 B I/O 1 A- Up ISA_SA0 28 B I/O 1 A- Up ISA_SA2 31 B I/O 1 A- Up ISA_SA3 32 B I/O 1 A- Up ISA_SA4 33 B I/O 1 A- Up ISA_SA5 34 B I/O 1 A- Up ISA_SA6 38 B I/O 1 A- Up ISA_SA7 39 B I/O 1 A- Up ISA_SA8 40 B I/O 1 A- Up ISA_SA9 23 B I/O 1 A- Up SJA_INTn --------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------- 47 A 1 1 1 1 COM -- Fast Up ISA_IRQ 14 A 11 1 1 1 COM -- Fast Up SJA_ALE 17 A 9 1 1 1 COM -- Fast Up SJA_CSn 15 A 2 1 1 1 COM -- Fast Up SJA_RDn 44 A 1 1 1 1 COM -- Fast Up SJA_RSTn 16 A 2 1 1 1 COM -- Fast Up SJA_WRn ------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ----------------------------------------------------------------- ----------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
PostFit_Equations
ISA_IRQ = SJA_INTn ; (1 pterm, 1 signal) SJA_ALE = !ISA_SA0 & !ISA_IOWn & !AEN & !ISA_SA2 & !ISA_SA3 & ISA_SA9 & ISA_SA8 & !ISA_SA7 & !ISA_SA6 & ISA_SA5 & ISA_SA4 ; (1 pterm, 11 signals) SJA_CSn = !( !AEN & !ISA_SA2 & !ISA_SA3 & ISA_SA9 & ISA_SA8 & !ISA_SA7 & !ISA_SA6 & ISA_SA5 & ISA_SA4 ) ; (1 pterm, 9 signals) SJA_RDn = !( ISA_SA0 & !ISA_IORn ) ; (1 pterm, 2 signals) SJA_RSTn = !ISA_RSTDRV ; (1 pterm, 1 signal) SJA_WRn = !( ISA_SA0 & !ISA_IOWn ) ; (1 pterm, 2 signals)